Panelists repeatedly highlighted that AI compute scaling is dramatically outpacing traditional Moore’s Law transistor ...

End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance” was published by researchers at KAIST, Panmnesia ...

Kalinagaswamy: Both have their own challenges. Scale-up may have hundreds of GPUs or accelerators, and they have to work in a scale-up network. Scale-out is point-to-point. They cannot make that many ...

Nvidia’s data center revenues have skyrocketed, and hyperscaler capital expenditures soared past $70B in 2025, about double ...

EDA produces a lot of data, but how useful is that for AI to consume? The industry looks at new ways to help AI do a better job.

The industry’s response is to split compute, memory, and I/O across dies, XPU chiplets are pushing toward the reticle limit, and stitch it all together with high‑bandwidth, energy‑efficient die‑to‑die ...

Designing and deploying DSPs FPGAs aren’t the only programmable hardware option, or the only option challenged by AI. While AI makes it easier to design DSPs, there are rising complexities due to the ...

Cadence’s Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor ...

A new technical paper, “Extreme optical nonlinearities unveiled by ultrafast laser filamentation in semiconductors,” was ...

Researchers from Rice University developed a bottom-up microwave plasma chemical vapor deposition method for growing patterned diamond surfaces that could help decrease operating temperatures in ...

A new technical paper, “3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography,” was published by researchers at Cornell University, ASM ...

Demand for higher performance in audio is rising as human-machine interactions increase on the edge. That means more processing elements, and more challenges in keeping data consistent across those ...