IEEE

A 10-bit 1-MS/s Low-Power SAR ADC with an Integrated Buffer in Dual Sample-and-Hold Architecture

Abstract: This paper presents a low-power design of a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an integrated buffer. A dual sample-and-hold architecture is ...
IEEE

An 88.8dB-SNDR 6-MS/s Pipelined SAR ADC with A Closed-Loop Dynamic Amplifier Featuring Highly-Linear Full-Scale Output Swing

Abstract: This paper presents a pipelined SAR ADC with a two-stage closed-loop residue amplifier (RA). The proposed RA incorporates a floating gm-ratio-based amplifier (FGA) as the first stage and a ...